The Interrupt Enable register lets you read and set a bit mask that disables or enables interrupts in the Amiga. This information is also valid for INTREQ and their read-only equivalents INTENAR and INTREQR.
15SET/CLR0=clear, 1=set bits that are set to 1 below
14INTENEnable interrupts below (master toggle)
13EXTERLevel 6 External interrupt
12DSKSYNLevel 5 Disk Sync value found
11RBFLevel 5 Receive Buffer Full (serial port)
10AUD3Level 4 Audio Interrupt channel 3
09AUD2Level 4 Audio Interrupt channel 2
08AUD1Level 4 Audio Interrupt channel 1
07AUD0Level 4 Audio Interrupt channel 0
06BLITLevel 3 Blitter Interrupt
05VERTBLevel 3 Vertical Blank Interrupt
04COPERLevel 3 Copper Interrupt
03PORTSLevel 2 CIA Interrupt (I/O ports and timers)
02SOFTLevel 1 Software Interrupt
01DSKBLKLevel 1 Disk Block Finished Interuppt
00TBELevel 1 Transmit Buffer Empty Interrupt (serial port)

You set and clear bits in the same way as you do for DMACON. Learn more about interrupt programming on