Custom Chip Register List

This is a listing of the Amiga custom registers housed inside the Agnus that control the various custom chips in the OCS, ECS, and AGA chipsets.
This is the basis of hardware programming - you use these registers (and the CIA registers) to control all of the computer hardware. Click a register description to read more.

How to access the registers

Most of the registers are write-only - they control the chips' behavior. For a few of them, there are corresponding read-only registers at another address (such as INTENA and INTENAR) where the R signifies that it can be read.
Don't read a write-only register, and don't write to a read-only register!

Special registers

A few are 'trigger' registers that start things, such as BLTSIZE which starts the blitter and COPJMP which starts the copper.
Some write-only registers have a special clear/set function in bit 15. This means the rest of the value written is a bitpattern mask, where bits are cleared if bit 15=0 and set if bit 15=1. Where the mask bits are 0, the corresponding bits are unaffected.
For example, this sets bits 10 and 6 to give the Blitter priority over the CPU and enable Blitter DMA in DMACON:
move.w #$8440,$dff096

While this clears the audio DMA bits of all four audio channels in DMACON:
move.w #$000f,$dff096

Both the CPU and the Copper can read and write these registers. In the case of the Copper, see the CDANG bit.
RegisterNamedescription
$dff000BLTDDATBlitter destination early read (unusable)
$dff002DMACONRDMA control (and blitter status) read
$dff004VPOSRRead vertical raster position bit 9 (and interlace odd/even frame)
$dff006VHPOSRRest of raster XY position - High byte: vertical, low byte: horizontal
$dff008DSKDATRDisk data early read (unusable)
$dff00aJOY0DATJoystick/mouse 0 data
$dff00cJOT1DATJoystick/mouse 1 data
$dff00eCLXDATPoll (read and clear) sprite collision state
$dff010ADKCONRAudio, disk control register read
$dff012POT0DATPot counter pair 0 data
$dff014POT1DATPot counter pair 1 data
$dff016POTGORPot pin data read
$dff018SERDATRSerial port data and status read
$dff01aDSKBYTRDisk data byte and status read
$dff01cINTENARInterrupt enable bits read
$dff01eINTREQRInterrupt request bits read
$dff020DSKPTHDisk track buffer pointer (high 5 bits)
$dff022DSKPTLDisk track buffer pointer (low 15 bits)
$dff024DSKLENDisk track buffer length
$dff026DSKDATDisk DMA data write
$dff028REFPTRAGA: Refresh pointer
$dff02aVPOSWWrite vert most sig. bits (and frame flop)
$dff02cVHPOSWWrite vert and horiz pos of beam
$dff02eCOPCONCoprocessor control register (CDANG)
$dff030SERDATSerial port data and stop bits write
$dff032SERPERSerial port period and control
$dff034POTGOPot count start, pot pin drive enable data
$dff036JOYTESTWrite to all 4 joystick/mouse counters at once
$dff038STREQUStrobe for horiz sync with VBLANK and EQU
$dff03aSTRVBLStrobe for horiz sync with VBLANK
$dff03cSTRHORStrobe for horiz sync
$dff03eSTRLONGStrobe for identification of long/short horiz line
$dff040BLTCON0Blitter control reg 0
$dff042BLTCON1Blitter control reg 1
$dff044BLTAFWMBlitter first word mask for source A
$dff046BLTALWMBlitter last word mask for source A
$dff048BLTCPTHBlitter pointer to source C (high 5 bits)
$dff04aBLTCPTLBlitter pointer to source C (low 15 bits)
$dff04cBLTBPTHBlitter pointer to source B (high 5 bits)
$dff04eBLTBPTLBlitter pointer to source B (low 15 bits)
$dff050BLTAPTHBlitter pointer to source A (high 5 bits)
$dff052BLTAPTLBlitter pointer to source A (low 15 bits)
$dff054BLTDPTHBlitter pointer to destination D (high 5 bits)
$dff056BLTDPTLBlitter pointer to destination D (low 15 bits)
$dff058BLTSIZEBlitter start and size (win/width, height)
$dff05aBLTCON0LBlitter control 0 lower 8 bits (minterms)
$dff05cBLTSIZVBlitter V size (for 15 bit vert size)
$dff05eBLTSIZHECS: Blitter H size & start (for 11 bit H size)
$dff060BLTCMODBlitter modulo for source C
$dff062BLTBMODBlitter modulo for source B
$dff064BLTAMODBlitter modulo for source A
$dff066BLTDMODBlitter modulo for destination D
$dff068RESERVEDReserved
$dff06aRESERVEDReserved
$dff06cRESERVEDReserved
$dff06eRESERVEDReserved
$dff070BLTCDATBlitter source C data reg
$dff072BLTBDATBlitter source B data reg
$dff074BLTADATBlitter source A data reg
$dff076RESERVEDReserved
$dff078SPRHDATAGA: Ext logic UHRES sprite pointer and data identifier
$dff07aBPLHDATAGA: Ext logic UHRES bit plane identifier
$dff07cLISAIDAGA: Chip revision level for Denise/Lisa
$dff07eDSKSYNCDisk sync pattern
$dff080COP1LCHWrite Copper pointer 1 (high 5 bits)
$dff082COP1LCLWrite Copper pointer 1 (low 15 bits)
$dff084COP2LCHWrite Copper pointer 2 (high 5 bits)
$dff086COP2LCLWrite Copper pointer 2 (low 15 bits)
$dff088COPJMP1Trigger Copper 1 (any value)
$dff08aCOPJMP2Trigger Copper 2 (any value)
$dff08cCOPINSCoprocessor inst fetch identify
$dff08eDIWSTRTDisplay window start (upper left vert-hor pos)
$dff090DIWSTOPDisplay window stop (lower right vert-hor pos)
$dff092DDFSTRTDisplay bitplane data fetch start.hor pos
$dff094DDFSTOPDisplay bitplane data fetch stop.hor pos
$dff096DMACONDMA control write (clear or set)
$dff098CLXCONWrite Sprite collision control bits
$dff09aINTENAInterrupt enable bits (clear or set bits)
$dff09cINTREQInterrupt request bits (clear or set bits)
$dff09eADKCONAudio, disk and UART control
$dff0a0AUD0LCHAudio channel 0 pointer (high 5 bits)
$dff0a2AUD0LCLAudio channel 0 pointer (low 15 bits)
$dff0a4AUD0LENAudio channel 0 length
$dff0a6AUD0PERAudio channel 0 period
$dff0a8AUD0VOLAudio channel 0 volume
$dff0aaAUD0DATAudio channel 0 data
$dff0acRESERVEDReserved
$dff0aeRESERVEDReserved
$dff0b0AUD1LCHAudio channel 1 pointer (high 5 bits)
$dff0b2AUD1LCLAudio channel 1 pointer (low 15 bits)
$dff0b4AUD1LENAudio channel 1 length
$dff0b6AUD1PERAudio channel 1 period
$dff0b8AUD1VOLAudio channel 1 volume
$dff0baAUD1DATAudio channel 1 data
$dff0bcRESERVEDReserved
$dff0beRESERVEDReserved
$dff0c0AUD2LCHAudio channel 2 pointer (high 5 bits)
$dff0c2AUD2LCLAudio channel 2 pointer (low 15 bits)
$dff0c4AUD2LENAudio channel 2 length
$dff0c6AUD2PERAudio channel 2 period
$dff0c8AUD2VOLAudio channel 2 volume
$dff0caAUD2DATAudio channel 2 data
$dff0ccRESERVEDReserved
$dff0ceRESERVEDReserved
$dff0d0AUD3LCHAudio channel 3 pointer (high 5 bits)
$dff0d2AUD3LCLAudio channel 3 pointer (low 15 bits)
$dff0d4AUD3LENAudio channel 3 length
$dff0d6AUD3PERAudio channel 3 period
$dff0d8AUD3VOLAudio channel 3 volume
$dff0daAUD3DATAudio channel 3 data
$dff0dcRESERVEDReserved
$dff0deRESERVEDReserved
$dff0e0BPL1PTHBitplane pointer 1 (high 5 bits)
$dff0e2BPL1PTLBitplane pointer 1 (low 15 bits)
$dff0e4BPL2PTHBitplane pointer 2 (high 5 bits)
$dff0e6BPL2PTLBitplane pointer 2 (low 15 bits)
$dff0e8BPL3PTHBitplane pointer 3 (high 5 bits)
$dff0eaBPL3PTLBitplane pointer 3 (low 15 bits)
$dff0ecBPL4PTHBitplane pointer 4 (high 5 bits)
$dff0eeBPL4PTLBitplane pointer 4 (low 15 bits)
$dff0f0BPL5PTHBitplane pointer 5 (high 5 bits)
$dff0f2BPL5PTLBitplane pointer 5 (low 15 bits)
$dff0f4BPL6PTHBitplane pointer 6 (high 5 bits)
$dff0f6BPL6PTLBitplane pointer 6 (low 15 bits)
$dff0f8BPL7PTHAGA: Bitplane pointer 7 (high 5 bits)
$dff0faBPL7PTLAGA: Bitplane pointer 7 (low 15 bits)
$dff0fcBPL8PTHAGA: Bitplane pointer 8 (high 5 bits)
$dff0feBPL8PTLAGA: Bitplane pointer 8 (low 15 bits)
$dff100BPLCON0Bitplane depth and screen mode)
$dff102BPLCON1Bitplane/playfield horizontal scroll values
$dff104BPLCON2Sprites vs. Playfields priority
$dff106BPLCON3AGA: Bitplane control reg (enhanced features)
$dff108BPL1MODBitplane modulo (odd planes)
$dff10aBPL2MODBitplane modulo (even planes)
$dff10cBPLCON4AGA: Bitplane control reg (bitplane & sprite masks)
$dff10eCLXCON2AGA: Write Extended sprite collision control bits
$dff110BPL1DATBitplane 1 data (parallel to serial convert)
$dff112BPL2DATBitplane 2 data (parallel to serial convert)
$dff114BPL3DATBitplane 3 data (parallel to serial convert)
$dff116BPL4DATBitplane 4 data (parallel to serial convert)
$dff118BPL5DATBitplane 5 data (parallel to serial convert)
$dff11aBPL6DATBitplane 6 data (parallel to serial convert)
$dff11cBPL7DATAGA: Bitplane 7 data (parallel to serial convert)
$dff11eBPL8DATAGA: Bitplane 8 data (parallel to serial convert)
$dff120SPR0PTHSprite 0 pointer (high 5 bits)
$dff122SPR0PTLSprite 0 pointer (low 15 bits)
$dff124SPR1PTHSprite 1 pointer (high 5 bits)
$dff126SPR1PTLSprite 1 pointer (low 15 bits)
$dff128SPR2PTHSprite 2 pointer (high 5 bits)
$dff12aSPR2PTLSprite 2 pointer (low 15 bits)
$dff12cSPR3PTHSprite 3 pointer (high 5 bits)
$dff12eSPR3PTLSprite 3 pointer (low 15 bits)
$dff130SPR4PTHSprite 4 pointer (high 5 bits)
$dff132SPR4PTLSprite 4 pointer (low 15 bits)
$dff134SPR5PTHSprite 5 pointer (high 5 bits)
$dff136SPR5PTLSprite 5 pointer (low 15 bits)
$dff138SPR6PTHSprite 6 pointer (high 5 bits)
$dff13aSPR6PTLSprite 6 pointer (low 15 bits)
$dff13cSPR7PTHSprite 7 pointer (high 5 bits)
$dff13eSPR7PTLSprite 7 pointer (low 15 bits)
$dff140SPR0POSSprite 0 vert-horiz start pos data
$dff142SPR0CTLSprite 0 position and control data
$dff144SPR0DATASprite 0 low bitplane data
$dff146SPR0DATBSprite 0 high bitplane data
$dff148SPR1POSSprite 1 vert-horiz start pos data
$dff14aSPR1CTLSprite 1 position and control data
$dff14cSPR1DATASprite 1 low bitplane data
$dff14eSPR1DATBSprite 1 high bitplane data
$dff150SPR2POSSprite 2 vert-horiz start pos data
$dff152SPR2CTLSprite 2 position and control data
$dff154SPR2DATASprite 2 low bitplane data
$dff156SPR2DATBSprite 2 high bitplane data
$dff158SPR3POSSprite 3 vert-horiz start pos data
$dff15aSPR3CTLSprite 3 position and control data
$dff15cSPR3DATASprite 3 low bitplane data
$dff15eSPR3DATBSprite 3 high bitplane data
$dff160SPR4POSSprite 4 vert-horiz start pos data
$dff162SPR4CTLSprite 4 position and control data
$dff164SPR4DATASprite 4 low bitplane data
$dff166SPR4DATBSprite 4 high bitplane data
$dff168SPR5POSSprite 5 vert-horiz start pos data
$dff16aSPR5CTLSprite 5 position and control data
$dff16cSPR5DATASprite 5 low bitplane data
$dff16eSPR5DATBSprite 5 high bitplane data
$dff170SPR6POSSprite 6 vert-horiz start pos data
$dff172SPR6CTLSprite 6 position and control data
$dff174SPR6DATASprite 6 low bitplane data
$dff176SPR6DATBSprite 6 high bitplane data
$dff178SPR7POSSprite 7 vert-horiz start pos data
$dff17aSPR7CTLSprite 7 position and control data
$dff17cSPR7DATASprite 7 low bitplane data
$dff17eSPR7DATBSprite 7 high bitplane data
$dff180COLOR00Palette color 00
$dff182COLOR01Palette color 1
$dff184COLOR02Palette color 2
$dff186COLOR03Palette color 3
$dff188COLOR04Palette color 4
$dff18aCOLOR05Palette color 5
$dff18cCOLOR06Palette color 6
$dff18eCOLOR07Palette color 7
$dff190COLOR08Palette color 8
$dff192COLOR09Palette color 9
$dff194COLOR10Palette color 10
$dff196COLOR11Palette color 11
$dff198COLOR12Palette color 12
$dff19aCOLOR13Palette color 13
$dff19cCOLOR14Palette color 14
$dff19eCOLOR15Palette color 15
$dff1a0COLOR16Palette color 16
$dff1a2COLOR17Palette color 17
$dff1a4COLOR18Palette color 18
$dff1a6COLOR19Palette color 19
$dff1a8COLOR20Palette color 20
$dff1aaCOLOR21Palette color 21
$dff1acCOLOR22Palette color 22
$dff1aeCOLOR23Palette color 23
$dff1b0COLOR24Palette color 24
$dff1b2COLOR25Palette color 25
$dff1b4COLOR26Palette color 26
$dff1b6COLOR27Palette color 27
$dff1b8COLOR28Palette color 28
$dff1baCOLOR29Palette color 29
$dff1bcCOLOR30Palette color 30
$dff1beCOLOR31Palette color 31
$dff1c0HTOTALAGA: Highest number count in horiz line (VARBEAMEN = 1)
$dff1c2HSSTOPAGA: Horiz line pos for HSYNC stop
$dff1c4HBSTRTAGA: Horiz line pos for HBLANK start
$dff1c6HBSTOPAGA: Horiz line pos for HBLANK stop
$dff1c8VTOTALAGA: Highest numbered vertical line (VARBEAMEN = 1)
$dff1caVSSTOPAGA: Vert line for Vsync stop
$dff1ccVBSTRTAGA: Vert line for VBLANK start
$dff1ceVBSTOPAGA: Vert line for VBLANK stop
$dff1d0SPRHSTRTAGA: UHRES sprite vertical start
$dff1d2SPRHSTOPAGA: UHRES sprite vertical stop
$dff1d4BPLHSTRTAGA: UHRES bit plane vertical start
$dff1d6BPLHSTOPAGA: UHRES bit plane vertical stop
$dff1d8HHPOSWAGA: DUAL mode hires H beam counter write
$dff1daHHPOSRAGA: DUAL mode hires H beam counter read
$dff1dcBEAMCON0Beam counter control register
$dff1deHSSTRTAGA: Horizontal sync start (VARHSY)
$dff1e0VSSTRTAGA: Vertical sync start (VARVSY)
$dff1e2HCENTERAGA: Horizontal pos for vsync on interlace
$dff1e4DIWHIGHAGA: Display window upper bits for start/stop
$dff1e6BPLHMODAGA: UHRES bit plane modulo
$dff1e8SPRHPTHAGA: UHRES sprite pointer (high 5 bits)
$dff1eaSPRHPTLAGA: UHRES sprite pointer (low 15 bits)
$dff1ecBPLHPTHAGA: VRam (UHRES) bitplane pointer (high 5 bits)
$dff1eeBPLHPTLAGA: VRam (UHRES) bitplane pointer (low 15 bits)
$dff1f0RESERVEDReserved
$dff1f2RESERVEDReserved
$dff1f4RESERVEDReserved
$dff1f6RESERVEDReserved
$dff1f8RESERVEDReserved
$dff1faRESERVEDReserved
$dff1fcFMODEAGA: Write Fetch mode (0=OCS compatible)
$dff1feNO-OPNo operation/NULL (Copper NOP instruction)